Pulse width modulation is widely used in areas of power regulation and telecommunications. A simple digital pulse width modulator (DPWM) may include a counter and a comparator. A so-called “hybrid DPWM” may include a counter-based circuit (or a counter logic) and a delay-locked loop (DLL). The hybrid DPWM may achieve higher time resolution without using a high frequency clock signal because the DLL may subdivide a clock period via multiple delay elements. The counter logic may generate a control signal based on the duty cycle specific to the DPWM. The control signal may then propagate through the multiple delay elements of the DLL. The output of the DLL may be converted into a pulse width modulated signal (output signal) that may be used by a voltage regulator (VR) to control the voltage applied to a load.
A hybrid DPWM may use one or more subtractors, or logics that are configured to perform subtraction operations, to generate the control signal based on the duty cycle of the DPWM. Typically, a subtractor or subtraction logic may occupy a relatively significant amount of area and/or require a relatively significant amount of power to operate. Further, a subtractor or subtraction logic may limit the switching frequency of the VR, of which the DPWM may be supplying a pulse width modulated signal to.